Cetinkaya, H. Et Al. 2018. A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , (Bordeaux, France), 277-280.

Cetinkaya, H., ZEKİ, A., Girgin, A., Karabeyoglu, E. D., & Karalar, T. C., (2018). A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs . 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp.277-280). Bordeaux, France

Cetinkaya, Hakan Et Al. "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs," 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, France, 2018

Cetinkaya, Hakan Et Al. "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs." 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Bordeaux, France, pp.277-280, 2018

Cetinkaya, H. Et Al. (2018) . "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs." 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Bordeaux, France, pp.277-280.

@conferencepaper{conferencepaper, author={Hakan Cetinkaya Et Al. }, title={A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs}, congress name={25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, city={Bordeaux}, country={France}, year={2018}, pages={277-280} }