N. Mentens Et Al. , "An FPGA Implementation of a Montgomery multiplier over GF 2 m," 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) , pp.121-128, 2004
Mentens, N. Et Al. 2004. An FPGA Implementation of a Montgomery multiplier over GF 2 m. 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) , 121-128.
Mentens, N., ÖRS YALÇIN, S. B., Preneel, B., & Vandewalle, J., (2004). An FPGA Implementation of a Montgomery multiplier over GF 2 m . 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) (pp.121-128).
Mentens, Nele Et Al. "An FPGA Implementation of a Montgomery multiplier over GF 2 m," 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS), 2004
Mentens, Nele Et Al. "An FPGA Implementation of a Montgomery multiplier over GF 2 m." 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) , pp.121-128, 2004
Mentens, N. Et Al. (2004) . "An FPGA Implementation of a Montgomery multiplier over GF 2 m." 7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) , pp.121-128.
@conferencepaper{conferencepaper, author={Nele Mentens Et Al. }, title={An FPGA Implementation of a Montgomery multiplier over GF 2 m}, congress name={7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS)}, city={}, country={}, year={2004}, pages={121-128} }