S. Parvin And M. Altun, "Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates," IEEE ACCESS , vol.7, pp.163939-163947, 2019
Parvin, S. And Altun, M. 2019. Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates. IEEE ACCESS , vol.7 , 163939-163947.
Parvin, S., & Altun, M., (2019). Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates. IEEE ACCESS , vol.7, 163939-163947.
Parvin, Sajjad, And Mustafa Altun. "Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates," IEEE ACCESS , vol.7, 163939-163947, 2019
Parvin, Sajjad And Altun, Mustafa. "Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates." IEEE ACCESS , vol.7, pp.163939-163947, 2019
Parvin, S. And Altun, M. (2019) . "Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates." IEEE ACCESS , vol.7, pp.163939-163947.
@article{article, author={Sajjad Parvin And author={Mustafa Altun}, title={Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates}, journal={IEEE ACCESS}, year=2019, pages={163939-163947} }