S. Aygün Et Al. , "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration," The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , Roma, Italy, pp.1-5, 2017
Aygün, S. Et Al. 2017. 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration. The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , (Roma, Italy), 1-5.
Aygün, S., Kouhalvandi, L., & Güneş, E. O., (2017). 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration . The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 (pp.1-5). Roma, Italy
Aygün, Sercan, Lida Kouhalvandi, And Ece Olcay Güneş. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration," The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017, Roma, Italy, 2017
Aygün, Sercan Et Al. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , Roma, Italy, pp.1-5, 2017
Aygün, S. Kouhalvandi, L. And Güneş, E. O. (2017) . "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , Roma, Italy, pp.1-5.
@conferencepaper{conferencepaper, author={Sercan Aygün Et Al. }, title={1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration}, congress name={The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017}, city={Roma}, country={Italy}, year={2017}, pages={1-5} }