AYGÜN, S. Et Al. 2018. 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration. International Journal of Advancement in Electronics and Electrical Engineering , 1-5.

AYGÜN, S., KOUHALVANDİ, L., & GÜNEŞ, E. O., (2018). 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration. International Journal of Advancement in Electronics and Electrical Engineering , 1-5.

AYGÜN, SERCAN, LİDA KOUHALVANDİ, And Ece Olcay Güneş. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration," International Journal of Advancement in Electronics and Electrical Engineering , 1-5, 2018

AYGÜN, SERCAN Et Al. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." International Journal of Advancement in Electronics and Electrical Engineering , pp.1-5, 2018

AYGÜN, S. KOUHALVANDİ, L. And GÜNEŞ, E. O. (2018) . "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." International Journal of Advancement in Electronics and Electrical Engineering , pp.1-5.

@article{article, author={SERCAN AYGÜN Et Al. }, title={1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration}, journal={International Journal of Advancement in Electronics and Electrical Engineering}, year=2018, pages={1-5} }