Image Filtering Processor and Its Applications

Bagbaba A. Ç., Ors B., Erozan A. T.

22nd IEEE Signal Processing and Communications Applications Conference (SIU), Trabzon, Türkiye, 23 - 25 Nisan 2014, ss.2011-2014 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/siu.2014.6830653
  • Basıldığı Şehir: Trabzon
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.2011-2014
  • İstanbul Teknik Üniversitesi Adresli: Evet

Özet

Nowadays, low cost, flexible, and high performance hardware-software co-design implementation of widely used image filtering methods is very important. In this work, image filtering processor is implemented through convolution, designed in Verilog Hardware Description Language, and softcore microprocessor. Microprocessor is synthesized on FPGA and removing of salt and pepper noises is examined. Convolution hardware is designed with and without D5P48 slice, which is dedicated hardware in FPGA, and obtained datas are compared. Also, synthesize of softcore microprocessor on FPGA is implemented for these two design and obtained datas are compared. Finally, one of selected basic algorithm is implemented on co-design and PSNR values are given.