A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process

As D. E., Yelten M. B.

INTEGRATION-THE VLSI JOURNAL, vol.88, pp.278-285, 2023 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 88
  • Publication Date: 2023
  • Doi Number: 10.1016/j.vlsi.2022.09.010
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, PASCAL, Aerospace Database, Applied Science & Technology Source, Communication Abstracts, Computer & Applied Sciences, INSPEC, Metadex, zbMATH, Civil Engineering Abstracts
  • Page Numbers: pp.278-285
  • Keywords: Ultra-low-power, Linearity improvement LNA, Complementary metal-oxide-semiconductor (CMOS), Intermodulation distortion (IMD), Linearization, RF circuit, LOW-NOISE AMPLIFIER, DESIGN
  • Istanbul Technical University Affiliated: Yes


This paper focuses on designing low-power, low-noise amplifiers (LNA) performances. Different LNA topologies operating with sub-mW power consumption at 2.4 GHz have been implemented in a commercial 40 nm CMOS process. The LNA1 (cascode common source LNA) has a voltage gain of 12.22 dB, a noise figure (NF) of 4.35 dB, and a third-order input intercept point (IIP3) of -12.68 dBm at 995.6 mu W while the proposed LNA2 with improved linearity has a 5.68 dB gain, 5.13 dB NF, and a -0.12 dBm IIP3. The difference between both final designs, which consist of improved linearity and gain, stems from the location of the gate inductance (Lg) in the chip. The proposed LNA3 with an on-chip Lg has a voltage gain of 11.1 dB, an NF of 4.27 dB, and an IIP3 of-0.82 dBm. Moreover, the proposed LNA4 with an off-chip Lg has 10.31 dB voltage gain, 3.68 dB NF, and 0.89 dBm IIP3 at 989.6 mu W in post-layout simulations. Comparing the LNAs, the proposed LNA4 with an off-chip Lg has the best figure-of-merit (FOM). This work aims to achieve improved linearity figures at sub-mW power.