DIGITAL DESIGN OF SKELETONIZATION


ATAY M., Yalcin M. E.

22nd IEEE Signal Processing and Communications Applications Conference (SIU), Trabzon, Turkey, 23 - 25 April 2014, pp.718-721 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/siu.2014.6830330
  • City: Trabzon
  • Country: Turkey
  • Page Numbers: pp.718-721

Abstract

In this study a real time skeletonization system is implemented on FPGA. Skeletonization forms the backbone of many tracking and matching applications in image processing. The computational complexity of the skeletonization algorithms highly increases to reach a performance close to perfect skeleton. This complexity makes it impossible for the systems to cope with real time requirements. Thus, in this work an FPGA suitable algorithm is elected for the implementation and the algorithm is extended by adding new rules to improve the performace of the output skeletons. A fully parallelized architecture is proposed to implement the extended skeleton extraction algorithm on FPGA. Performance of the novel algorithm is evaluated according to the widely acknowledged performance measures for skeletonization research. Resource utilization and timing performance of the FPGA implementation are investigated for comparison with similar systems in literature.