Akademik Veri Yönetim Sistemi
10th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Türkiye, 30 Kasım - 02 Aralık 2017, ss.437-441
In this paper, we propose a template-based multimedia processor array and its design framework. The configurable processor array is designed for low-cost, low-power image/video processing applications. Each processor in the array is template-based and implemented by considering the nature and specifications of image/video processing domain. The framework can set the size of the network and the parameters of the building blocks of each processor. Hence, the generated architecture occupies only the necessary amount of logic. To show the scalability and the performance of the design, different instances of the architecture implementing four test applications are generated. We have obtained better or comparable results in terms of energy consumption, throughput and area occupation compared to that of the similar architectures in literature.