A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs


Cetinkaya H., ZEKİ A., Girgin A., Karabeyoglu E. D. , Karalar T. C.

25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, France, 9 - 12 December 2018, pp.277-280 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Bordeaux
  • Country: France
  • Page Numbers: pp.277-280

Abstract

This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 mu m x 360 mu m silicon area, is realized in a SiGe BiCMOS 0.13 mu m process.