Capacitor multiplier with high multiplication factor for integrated low pass filter of biomedical applications using DTMOS technique


ALAYBEYOĞLU E., Kuntman H.

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, vol.107, pp.291-297, 2019 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 107
  • Publication Date: 2019
  • Doi Number: 10.1016/j.aeue.2019.06.001
  • Title of Journal : AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
  • Page Numbers: pp.291-297

Abstract

In this work, capacitor multiplier circuit is designed for use in biomedical applications. The designed circuit operates with +/- 0.3 V supply voltage at very low quiescent current. The design of the proposed circuit is realized with DTMOS technique by using standard CMOS process. The designed circuit has a high multiplication factor and allows the integration of the capacitance of the low-pass filters required in low-frequency applications such as bio-medicals. At the same time, the proposed circuit has the low power consumption that should be in implantable devices. The proposed circuit is designed with 0.18 mu m TSMC technology in Cadence environment. (C) 2019 Elsevier GmbH. All rights reserved.