Reconfigurable OPB coprocessors for a microblaze self-reconfigurable SOC mapped on spartan-3 FPGAs


Canto E., Fons F., Lopez M.

32nd Annual Conference of the IEEE-Industrial-Electronics-Society, Paris, France, 7 - 10 November 2006, pp.3673-3674 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Paris
  • Country: France
  • Page Numbers: pp.3673-3674

Abstract

Dynamically reconfigurable FPGAs are usually based on internal SRAM configuration memory, that can be fully or partially written from an external device. One of their applications is to map reconfigurable coprocessors, so an external microprocessor can change during run-time the coprocessor mapped on a FPGA. Coprocessors can execute the time-critical tasks of an algorithm, while the general purpose microprocessor executes the rest of computations and controls the FPGA reconfiguration. Microblaze is a soft-core 32-bit microprocessor designed to be implemented as a part of a System-On-Chip (SOC) mapped on Xilinx FPGAs. The Xilinx EDK software allows designers to map a SOC composed of a Microblaze plus several OPB (On-chip Peripheral Bus) peripherals. But the EDK was not designed to allow reconfigurable OPB peripherals mapped on the FPGA device. This paper demonstrates that it is possible to design an self-reconfigurable SOC mapped on a low-cost Spartan-3 FPGA, where an area section is devoted to map several reconfigurable OPB coprocessors in a time-multiplexed way.