Statistical design of a multiplier using a low power square-law CMOS analog cell


Tarim T., Kuntman H., Ismail M.

XI Brazilian Symposium on Integrated Circuit Design (SBCCI 98), RIO JANEIRO, Brazil, 30 September - 03 October 1998, pp.191-194 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/sbcci.1998.715439
  • City: RIO JANEIRO
  • Country: Brazil
  • Page Numbers: pp.191-194

Abstract

The statistical design of a new multiplier using the square-law characteristics of MOS transistors in the saturation region is discussed in this paper. The multiplier is statistically robust and has a good yield. Initial simulation results of the circuit have been given and the offset current and nonlinearity of the multiplier have been statistically examined. Response Surface Methodology and Design of Experiment techniques were used as statistical VLSI design tools combined with the statistical MOS (SMOS) model. Device size optimization and yield enhancement have been demonstrated.