Scalable and Efficient Analog Parametric Fault Identification

Yelten M. B., NATARAJAN S., XUE B., GOTETİ P.

32nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San-Jose, Costa Rica, 18 - 21 November 2013, pp.387-392 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/iccad.2013.6691147
  • City: San-Jose
  • Country: Costa Rica
  • Page Numbers: pp.387-392
  • Keywords: test coverage, within-die variations, parametric faults, process variations, analog circuits, design for test
  • Istanbul Technical University Affiliated: No

Abstract

Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.