DESIGN OF NEW TINY CIRCUITS FOR AES ENCRYPTION ALGORITHM


DALMISLI K. V. , Ors B.

3rd International Conference on Signals, Circuits and Systems, Medenine, Tunus, 6 - 08 Kasım 2009, ss.565-569 identifier identifier

  • Doi Numarası: 10.1109/icscs.2009.5414191
  • Basıldığı Şehir: Medenine
  • Basıldığı Ülke: Tunus
  • Sayfa Sayıları: ss.565-569

Özet

Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.