Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays


Morgül M. C. , Peker F. , Altun M.

IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI), Pennsylvania, United States Of America, 11 - 13 July 2016, pp.437-442 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/isvlsi.2016.100
  • City: Pennsylvania
  • Country: United States Of America
  • Page Numbers: pp.437-442

Abstract

In this study, we introduce an accurate capacito-rresistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.