Research Information System
INTEGRATION-THE VLSI JOURNAL, vol.47, no.1, pp.30-37, 2014 (SCI-Expanded)
This paper presents the design of a low-drift, curvature-corrected bandgap voltage reference (BGR) realized in a 0.35 mu m 3.3 V triple-well CMOS technology having vertical NPN BJT transistors. The proposed circuit takes advantage of a block bulk isolation strategy improving the substrate noise sensitivity at the BGR output more than 100 dB up to 100 MHz. The simulated circuit achieves a mean temperature coefficient of 6.2 ppm/degrees C over the temperature range of -40 to 125 degrees C with 4.1 ppm/degrees C standard deviation without any trimming. The circuit operates down to 2 V and consumes 31.5 mu A from a single 3.3 V supply. Its line regulation is less than 0.07% per Volt while its supply voltage changes from 2 V to 3.6 V. The power supply rejection (PSR) of the circuit is -76.5 dB at 100 Hz. The peak-to-peak output noise is 4.66 mu V integrated within the frequency range of 0.1-10 Hz. The proposed circuit occupies an area of (515 mu m x 320 mu m) 0.165 mm(2). (C) 2013 Elsevier B.V. All rights reserved.