In this work a new structure of current mode min-max circuit using 0.18 mu m CMOS standard technology is presented. It is based on cascode current mirror and enjoys 30 NMOS transistors. A 1.8(V) power supply is applied and simulation results are prepared using HSPICE software with level 49 parameters (BSIM3v3). It has noticeable advantages like 0.9 percent error in maximum input signal amplitude, 0.88nS delay, and small chip die size area. To check the functionality of proposed circuit, different simulations have been performed. Also, layout pattern of min-max circuit is prepared by Cadence software. The achieved area of proposed circuit is less than 31 mu m(2).