Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance


Morgül M. C. , Frontini L., Tunali O., Anghel L., Ciriani V., Vatajelu E. I. , ...More

IEEE TRANSACTIONS ON NANOTECHNOLOGY, vol.20, pp.39-53, 2021 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 20
  • Publication Date: 2021
  • Doi Number: 10.1109/tnano.2020.3044017
  • Journal Name: IEEE TRANSACTIONS ON NANOTECHNOLOGY
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Aerospace Database, Biotechnology Research Abstracts, Chemical Abstracts Core, Communication Abstracts, Compendex, INSPEC, Metadex, Civil Engineering Abstracts
  • Page Numbers: pp.39-53
  • Istanbul Technical University Affiliated: Yes

Abstract

Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.