Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance


Morgül M. C., Frontini L., Tunali O., Anghel L., Ciriani V., Vatajelu E. I., ...Daha Fazla

IEEE TRANSACTIONS ON NANOTECHNOLOGY, cilt.20, ss.39-53, 2021 (SCI-Expanded) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 20
  • Basım Tarihi: 2021
  • Doi Numarası: 10.1109/tnano.2020.3044017
  • Dergi Adı: IEEE TRANSACTIONS ON NANOTECHNOLOGY
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Aerospace Database, Biotechnology Research Abstracts, Chemical Abstracts Core, Communication Abstracts, Compendex, INSPEC, Metadex, Civil Engineering Abstracts
  • Sayfa Sayıları: ss.39-53
  • İstanbul Teknik Üniversitesi Adresli: Evet

Özet

Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.