Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates

Parvin S., ALTUN M.

2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, 1 - 03 July 2019 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/iolts.2019.8854440
  • City: Rhodes, Greece
  • Istanbul Technical University Affiliated: Yes

Abstract

In reversible circuits, a fault as a change in logic value at a circuit node always alters an output logic value, so observability of faults at the output is 100%. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible circuits to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED). For this purpose we propose a new, fault preservative, and reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPCT, we ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node.