This paper presents a frequency multiplier employing a pseudo-differential charge-pump phase-locked loop (PDCPPLL) and a novel technique to maintain the 50% duty cycle at the output. A differential charge-pump PLL reduces the common-mode noise and alleviates unwanted secondary effects encountered in the single-ended architecture. Pseudo-differential PLLs do not involve common-mode feedback. Moreover, compared to single-ended counterparts, they offer improved noise suppression and leakage cancellation at the input of a voltage-controlled oscillator. A complete overview of the design will be provided along with simulations to prove its functionality and provide its sensitivity to process and temperature variations. The frequency multiplier is designed in 180 nm complementary-metal-oxide-semiconductor technology to operate at 560 MHz.