Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for Delta Sigma Modulator within the loop while preserving frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the disigner to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking precisely the output frequency to a control voltage. Implemented loop occupies an area of 650 mu m in 630 mu m in 0.35 mu m CMOS process and draws 383 mu A from a single 3.3V supply. It covers a frequency range of 4 - 70MHz with 76Hz resolution and has a measure phase noise performance of 104dBc/Hz at 1MHz offset with the worst spurious signal level of -70dBc.