Surrogate-Model-Based Analysis of Analog Circuits-Part II: Reliability Analysis

Yelten M. B., Franzon P. D., Steer M. B.

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol.11, no.3, pp.458-465, 2011 (SCI-Expanded) identifier identifier


This paper presents a reliability simulation framework based on surrogate modeling. A novel methodology has been developed, which integrates variability analysis with the reliability concepts by employing transistor drain-current surrogate models in terms of crucial process parameters, bias voltages, temperature, and time. Simulation techniques using these models enables exploration of the effects of time-based degradation on analog circuits. The analysis of a differential amplifier at the 65-nm technology node reveals that the dc current is reduced by around 10% in ten years. The tool is used to demonstrate how the biasing structures of analog circuits can be designed to boost aging resilience.