Akademik Veri Yönetim Sistemi
21st Signal Processing and Communications Applications Conference (SIU), CYPRUS, 24 - 26 Nisan 2013
In this work, design of an interpolation and modulation system to be used in next generation communication DACs (Digital to Analog Converters) is presented. First, the filters of the system are modeled using MATLAB. Second, digital design is done using Verilog language. Third, place and route is completed using CADENCE design tools and TSMC 0.18 mu m CMOS process. Finally, post place and route simulations are performed. It is seen that the design operates at 1.2 GSPS and provides 99 dB spurious free dynamic range (SFDR), consuming 1.826 W. The SFDR performance of the design is 9-14 dB higher than similar ICs on the market today.