A 4-transistor Euclidean distance cell for analog classifiers

Cilingiroglu U., Aksin D.

IEEE International Symposium on Circuits and Systems (ISCAS 98), Monterrey, Mexico, 31 May - 03 June 1998, pp.84-87 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Monterrey
  • Country: Mexico
  • Page Numbers: pp.84-87
  • Istanbul Technical University Affiliated: No


The areal efficiency of a high-throughput parallel classifier depends strongly on the area of the basic distance cell because classifier architectures contain a large array of such cells. For this reason, reducing the circuit complexity of a distance cell is expected to have a magnified impact on the overall size. A new squared Euclidean distance-cell configuration comprising four MOSFETs and two capacitors is proposed. The cell is based on symmetrical capacitive template storage and current-domain readout, which help reduce size while increasing speed and precision. A typical cell design in a mainstream 0.8 mu m CMOS technology occupies 17.2x21.9 (mu m(2)) silicon area representing an areal density of 2650 cells per square millimeter. The article includes a description and analysis of the circuit, identifies design constraints and presents an error analysis.