The areal efficiency of a high-throughput parallel classifier depends strongly on the area of the basic distance cell because classifier architectures contain a large array of such cells. For this reason, reducing the circuit complexity of a distance cell is expected to have a magnified impact on the overall size. A new squared Euclidean distance-cell configuration comprising four MOSFETs and two capacitors is proposed. The cell is based on symmetrical capacitive template storage and current-domain readout, which help reduce size while increasing speed and precision. A typical cell design in a mainstream 0.8 mu m CMOS technology occupies 17.2x21.9 (mu m(2)) silicon area representing an areal density of 2650 cells per square millimeter. The article includes a description and analysis of the circuit, identifies design constraints and presents an error analysis.