Precision improvement in current-mode winner-take-all circuits using gain-boasted regulated-cascode CMOS stages

Sekerkiran B., Cilingiroglu U.

2nd IEEE World Congress on Computational Intelligence (WCCI 98), Alaska, United States Of America, 4 - 09 May 1998, pp.553-556 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Alaska
  • Country: United States Of America
  • Page Numbers: pp.553-556
  • Istanbul Technical University Affiliated: No

Abstract

This paper presents a study on advantages and concerns of using gain-boosted regulated-cascoding technique in current-mode WTA circuits. For large scale integration and high frequency applications the use of MOS transistors with minimum feature size is a must. But modern MOS transistors having sub-micron channel length, exhibit pronounced channel-length modulation. This deficiency causes precision degradation in WTA circuits. With the use of gain-boosted regulated-cascoding technique, a very high precision can be achieved in current-mode WTA circuits formed using sub-micrometer transistors.