Differential Power Analysis resistant hardware implementation of the RSA cryptosystem


Bayam K. A. , Ors B.

IEEE International Symposium on Circuits and Systems, Washington, United States Of America, 18 - 21 May 2008, pp.3314-3315 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/iscas.2008.4542167
  • City: Washington
  • Country: United States Of America
  • Page Numbers: pp.3314-3315

Abstract

In this paper, RSA cryptosystem was implemented on an FPGA as resistant against Differential Power Analysis attacks. There are hardware and algorithmic countermeasures against power analysis attacks. This is the first FPGA realization of an algorithmic countermeasure which makes RSA resistant to power analysis attacks. Modular exponentiation is realized with Montgomery Modular Multiplication. The Montgomery modular multiplier has been realized with carry save adders. Carry save representation has been used throughout the RSA encryption algorithm. The protected implementation resulted in 66,66 MHz of clock frequency, 84,42 Kb/s of throughput, and 6,06 ms of total exponentiation time and occupied an area of 10986 slices with the use of the built-in block SelectRAM structure inside XCV1000E.