An FPGA Implementation of a Montgomery multiplier over GF 2 m

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Mentens N., ÖRS YALÇIN S. B. , Preneel B., Vandewalle J.

7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS), 18 - 21 April 2004, pp.121-128

• Publication Type: Conference Paper / Full Text
• Page Numbers: pp.121-128