An FPGA Implementation of a Montgomery multiplier over GF 2 m

Mentens N., ÖRS YALÇIN S. B. , Preneel B., Vandewalle J.

7th IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS), 18 - 21 Nisan 2004, ss.121-128

  • Sayfa Sayıları: ss.121-128