An Approach to Test Determination for Programmable Logic Arrays


Cvetkovic L., Tuba M.

9th WSEAS International Conference on Applied Informatics and Communications, Moscow, Rusya, 20 - 22 Ağustos 2009, ss.145-147 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: Moscow
  • Basıldığı Ülke: Rusya
  • Sayfa Sayıları: ss.145-147

Özet

In this paper we propose a fault model for Programmable Logic Array in which defects appear in programmable elements. The classical models by which the faults in PLA are described (stuck-at-fault, bridging faults and cross point fault model) do not describe the defects which can appear in the programmable elements of PLA. We propose a fault model for PLA in which programmable elements where faults appear get the signal values of permanent logic I or permanent logic 0. We also developed a procedure for detecting a multiple fault located at the programmable elements of PLA. The testing procedure makes use of the path sensitization method. It is illustrated by some examples. By the proposed procedure a number of stuck-at-faults, bridging faults and cross point faults are detected as well.