A Hardware Accelerated Packet Classifier Design for A Network Router Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Cik O., Yalçın M. E.

28th Signal Processing and Communications Applications Conference, SIU 2020, Gaziantep, Turkey, 5 - 07 October 2020 identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.1109/siu49456.2020.9302072
  • City: Gaziantep
  • Country: Turkey
  • Istanbul Technical University Affiliated: Yes


© 2020 IEEE.In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.