Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection


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Mousavikia S. K. , Gholizadehazari E., Mousazadeh M., Örs Yalçın S. B.

IEEE ACCESS, vol.10, pp.58151-58162, 2022 (Journal Indexed in SCI) identifier

  • Publication Type: Article / Article
  • Volume: 10
  • Publication Date: 2022
  • Doi Number: 10.1109/access.2022.3177743
  • Title of Journal : IEEE ACCESS
  • Page Numbers: pp.58151-58162
  • Keywords: Convolutional neural network, driver drowsiness detection, FPGA, hardware implementation, modified RiscV processor, IMPLEMENTATION

Abstract

This paper describes the design and implementation of a driver drowsiness detection (DDD) system using a modified RiscV processor on a field-programmable gate array (FPGA). To detect drowsiness, Convolutional Neural Network (CNN) is implemented on a RiscV processor. The CNN is trained to classify four primary driver's expressions, including distraction, natural, sleep, and yawn. The trained CNN accuracy is 81.07% on validation data. Furthermore, due to FPGA memory limitations, written C code for the trained CNN is optimized in numerous ways. Optimizations include the usage of dynamic fixed-point data types and dynamic memory allocations. On the other hand, the processor is modified by adding three custom instructions, including custom store, conv2d(2 x 2), and multiply and accumulation (MAC) to enhance the computation rate. As a result, the processor with custom store, conv2d(2 x 2), and MAC as custom instructions achieved the best result in terms of latency, with an improvement factor of 1.7 over the base processor and 1.25 over the processor with only custom store and multiply and accumulation (MAC) in exchange of slight increase in area.