Serial multiplier architectures over GF(2(n)) for elliptic curve cryptosystems


BATINA L., MENTENS N., Ors S. B. , PRENEEL B.

12th IEEE Mediterranean Electrotechnical Conference (MELECON 2004), Dubrovnik, Croatia, 12 - 15 May 2004, pp.779-782 identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/melcon.2004.1347047
  • City: Dubrovnik
  • Country: Croatia
  • Page Numbers: pp.779-782

Abstract

We present an FPGA implementation of a new multiplier for binary finite fields that combines two previously known methods. The multiplier is designed for polynomial bases which allow more flexibility in hardware and is dedicated to efficient implementations of elliptic curve cryptography. An extension to a digit-serial architecture is also sketched. For the introduced architecture we also discuss resistance to side-channel attacks.