12th IEEE Mediterranean Electrotechnical Conference (MELECON 2004), Dubrovnik, Hırvatistan, 12 - 15 Mayıs 2004, ss.779-782
We present an FPGA implementation of a new multiplier for binary finite fields that combines two previously known methods. The multiplier is designed for polynomial bases which allow more flexibility in hardware and is dedicated to efficient implementations of elliptic curve cryptography. An extension to a digit-serial architecture is also sketched. For the introduced architecture we also discuss resistance to side-channel attacks.