AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, cilt.63, sa.11, ss.992-997, 2009 (SCI-Expanded)
In this paper, a method to reduce the errors generated by the second order effects in the current-mode circuits employing MOS translinear loop is proposed. Using this method a square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed and presented. They are suitable for standard CMOS fabrication and analog systems. (c) 2008 Elsevier GmbH. All rights reserved.