Design considerations for CMOS digital circuits with improved hot-carrier reliability


Leblebici Y.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol.31, no.7, pp.1014-1024, 1996 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 31 Issue: 7
  • Publication Date: 1996
  • Doi Number: 10.1109/4.508215
  • Title of Journal : IEEE JOURNAL OF SOLID-STATE CIRCUITS
  • Page Numbers: pp.1014-1024

Abstract

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled, Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability, It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance, In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated, The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (r) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging, Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability.