A low voltage CMOS square law analog multiplier

Tarim T., Ismail M.

Southwest Symposium on Mixed-Signal Design (SSMSD 99), Arizona, Amerika Birleşik Devletleri, 11 - 13 Nisan 1999, ss.5-8 identifier identifier

  • Doi Numarası: 10.1109/ssmsd.1999.768581
  • Basıldığı Şehir: Arizona
  • Basıldığı Ülke: Amerika Birleşik Devletleri
  • Sayfa Sayıları: ss.5-8


A multiplier composed of a low voltage square-law CMOS cell is introduced in this paper. The analysis of the square-law cell is given. The multiplier operates in the saturation region with a fully balanced input signal. Initial simulations were done for 0.8 mu m n-well process using BSIM3 model parameters. The circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 99.4MHz and P-dis=1.5mW for a bias current of 120 mu A. The THD is less then -51dB and -49dB for fixed input voltages V3 and V1, respectively,for a 1MHz, 0.5V peak-to-peak sinusoidal input.