JITTER ANALYSIS OF A PHASE-LOCKED DIGITAL TIMING RECOVERY-SYSTEM


PANAYIRCI E.

IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION, vol.139, no.3, pp.267-275, 1992 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 139 Issue: 3
  • Publication Date: 1992
  • Doi Number: 10.1049/ip-i-2.1992.0037
  • Title of Journal : IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION
  • Page Numbers: pp.267-275

Abstract

An analytical approach is presented for the jitter performance of a timing recovery circuit consisting of a hard-limiter, an exclusive-or gate, followed by a second-order phase-locked loop. Exact expressions for the autocorrelation function and the power spectral density of the zero-crossing jitter in the data signal are derived, and then the phase jitter variance of the timing wave, generated at the output of the timing circuit, is obtained analytically as a function of various system parameters. Finally, numerical results and a comparative performance analysis show that considerable improvement can be achieved in jitter performance in addition to having the advantage of low cost and simple hardware implementation.