A non-autonomous chaotic circuit which is suitable for high-frequency IC realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincare map of the system passed the four basic tests of FIPS-140-1 test suite. We also have verified that the binary data obtained from the hardware realization of this continuous-time chaotic oscillator in the same way pass the full NIST random number test suite. Then, in order to increase the output throughput and the statistical quality of the generated bit sequences, we propose a TRNG design which uses a dual oscillator architecture with the proposed continuous-time chaotic oscillator. Finally we have experimentally verified that the binary data obtained by this oscillator sampling technique pass the tests of full NIST random number test suite for a higher throughput speed. While the throughput data rate obtained by using continuous-time chaotic oscillator alone is effectively 488 bps, it achieves 830 Kbps for the proposed TRNG design, which uses the dual oscillator architecture.