This study analyses and compares the most popular Montgomery multiplication algorithms for their power dissipation on FPGA devices. Among various architectures proposed for Montgomery multiplication, we pick the parallel, sequential and systolic variants as the most revealing ones for our experimental needs. The synthesis results indicate that the sequential setting with a single cell gives the most efficient employment of the algorithm for dynamic power dissipation. However, if the energy is considered the parallel architecture is the most appropriate choice. Our analyses provides a fair comparison of power consumption of Montgomery multiplication algorithms on FPGAs giving hints to the engineers realizing the core of the most popular methods used in public-key cryptographic systems such as RSA, Diffie-Hellman, ECC and others.