Creating Test Environment with UVM for SPI


Ustaoglu B. , Bagbaba A. C. , Ors B. , Erdem I.

23nd Signal Processing and Communications Applications Conference (SIU), Malatya, Turkey, 16 - 19 May 2015, pp.2373-2376 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/siu.2015.7130358
  • City: Malatya
  • Country: Turkey
  • Page Numbers: pp.2373-2376

Abstract

In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language System Verilog and creating test environment with UVM.