Linear transconductors using low voltage power square-law CMOS cells


Tarim T., Ismail M.

9th Great Lakes Symposium on VLSI (GLSVLSI 99), Michigan, United States Of America, 4 - 06 March 1999, pp.206-209 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/glsv.1999.757411
  • City: Michigan
  • Country: United States Of America
  • Page Numbers: pp.206-209

Abstract

Two transconductors composed of two square-law CMOS cells are introduced in this paper. The analysis of the cells is given. The transconductors operate in the saturation region with a fully balanced input signal. Simulations were done for 0.8 mu m n-well process using BSIM3 model parameters. The first circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 170MHz and P-dis = 1.17mW for a bias current of 120 mu A. The second transconductor has aimed to overcome the trade-off and to improve the performance: the circuit has a cutoff frequency of 236MHz and P-dis=1.74mW for the same bias current, however, it is possible to reduce the bias current, since the trade-off The transconductors have a THD of less then -56dB and -60dB, respectively for 1MHz, 0.5V peak-to-peak sinusoidal input. A comparison between the two circuit performances is given.