This paper presents surrogate modeling as a solution to variation-aware macromodeling, circuit design, and device modeling. A scalable and high-fidelity IO buffer macromodel is created by integrating surrogate modeling with a physically-based model structure. Circuit performance surrogate models with design and variation parameters are efficient for design space exploration and performance yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. Surrogate-based optimization has great potential to speed up complex circuit design.