Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation


Tunalı O., Morgul M. C. , Altun M.

IEEE MICRO, vol.38, no.5, pp.22-31, 2018 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 38 Issue: 5
  • Publication Date: 2018
  • Doi Number: 10.1109/mm.2018.053631138
  • Title of Journal : IEEE MICRO
  • Page Numbers: pp.22-31

Abstract

In this paper, we study defect-tolerant logic synthesis of memristor-based crossbar architectures. We propose a hybrid algorithm, combining heuristic and exact algorithms, that achieves perfect tolerance for 10-percent stuck-at open defect rates. Along with defect tolerance, we also consider area, delay, and power costs of the memristor crossbars to elaborate on two-level and multi-level logic designs.