Defect Tolerance in Diode, FET, and Four-Terminal Switch Based Nano-Crossbar Arrays


Tunali O., Altun M.

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Massachusetts, United States Of America, 8 - 10 July 2015, pp.82-87 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Massachusetts
  • Country: United States Of America
  • Page Numbers: pp.82-87

Abstract

In this paper, defect tolerance performance of switching nano-crossbar arrays is extensively studied. Three types of nanoarrays where each crosspoint behaves as a diode, FET, and four-terminal switch, are considered. For each crosspoint, both stuck-open and stuck-closed defect probabilities are independently taken into consideration. A fast heuristic algorithm using indexing and mapping techniques is proposed. The algorithm measures defect tolerance performances of the crossbar arrays that are expected to implement a certain given function. The algorithm's effectiveness is demonstrated on standard benchmark circuits that shows 99% accuracy compared with an exhaustive search. The benchmark results also show that not only the used technology, the nanoarray type, but more significantly the specifics of given functions affect defect tolerance performances.