A new method has been proposed to reduce the mobility degradation effect on square-law characteristic of the MOS transistor. This method has been applied to an analog multiplier to reduce the harmonic distortion. The analog multiplier designed operates with 5 V power supply. The linear operating range for each input is 3 V. In this operating range the circuit provides a total harmonic distortion of THD = 0.6% from X input to the output and THD = 0.5% from Y input to the output for operating as voltage controlled amplifier. Similarly, the 3 dB bandwidths are specified as 32 MHz and 34 MHz for X and Y inputs, respectively. The multiplier topology proposed allows extemal adjustment of the distortion, which can be considered as another important advantage of the circuit. The results show that the new method is effective for reducing distortion.