In this paper, CMOS realizations of exponential function generators are considered and it is shown that the inherent square-law characteristic of the CMOS can be effectively used to produce the required exponential characteristic. While many of the existing exponential function generators rely on complicated coefficient settings procedure, in order approach, the circuit inherently realizes the required approximating function. However, the additional errors due to square-law model limitation can be alleviated by using so-called cascade realization technique. The functionality of the design is confirmed with 65 nm CMOS process technology with +/- 0.5 V power supply in saturation region. In this design the power dissipation is 150 mu W. Simulation results proves the correctness of the theoretical analysis and proves the viability of the proposed structure.