A Folded Architecture for Hardware Implementation of a Neural Structure Using Izhikevich Model

Cagdas S., Şengör N. S.

31st International Conference on Artificial Neural Networks (ICANN), Bristol, İngiltere, 6 - 09 Eylül 2022, cilt.13531, ss.508-518 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Cilt numarası: 13531
  • Doi Numarası: 10.1007/978-3-031-15934-3_42
  • Basıldığı Şehir: Bristol
  • Basıldığı Ülke: İngiltere
  • Sayfa Sayıları: ss.508-518
  • Anahtar Kelimeler: Izhikevich, Neuromorphic circuits, FPGA, SNN, Folded architecture
  • İstanbul Teknik Üniversitesi Adresli: Evet

Özet

Neuromorphic systems are expected to equip a new paradigm in computation so that energy efficient, intelligent systems could be implemented easily. One way of fulfilling this aim is to design processes with Spiking Neural Networks (SNN). Here, we introduce an architecture to realize Izhikevich neuron model which ease the hardware implementation of large scale neural models. By using a folding method, we ensure that multiple operations of the same type are performed by one computing unit in a time multiplexed manner. In this way, we have achieved a design that uses hardware resources more efficiently, especially by saving multiplication, and allows more neurons to be implemented on the hardware. Finally, this architecture eliminates the necessity to allocate additional resources for implementing the synaptic dynamics of the neurons. Also, to present the effectiveness of the proposed architecture, a simple cerebellar granular layer structure is implemented on FPGA.