A Folded Architecture for Hardware Implementation of a Neural Structure Using Izhikevich Model


Cagdas S., Şengör N. S.

31st International Conference on Artificial Neural Networks (ICANN), Bristol, England, 6 - 09 September 2022, vol.13531, pp.508-518 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume: 13531
  • Doi Number: 10.1007/978-3-031-15934-3_42
  • City: Bristol
  • Country: England
  • Page Numbers: pp.508-518
  • Keywords: Izhikevich, Neuromorphic circuits, FPGA, SNN, Folded architecture
  • Istanbul Technical University Affiliated: Yes

Abstract

Neuromorphic systems are expected to equip a new paradigm in computation so that energy efficient, intelligent systems could be implemented easily. One way of fulfilling this aim is to design processes with Spiking Neural Networks (SNN). Here, we introduce an architecture to realize Izhikevich neuron model which ease the hardware implementation of large scale neural models. By using a folding method, we ensure that multiple operations of the same type are performed by one computing unit in a time multiplexed manner. In this way, we have achieved a design that uses hardware resources more efficiently, especially by saving multiplication, and allows more neurons to be implemented on the hardware. Finally, this architecture eliminates the necessity to allocate additional resources for implementing the synaptic dynamics of the neurons. Also, to present the effectiveness of the proposed architecture, a simple cerebellar granular layer structure is implemented on FPGA.