Design of A 100MHz 64-Point FFT Processor in 0.35 mu m Standard CMOS Technology

Mojarad H., Hajghassem H.

8th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics, İstanbul, Turkey, 30 May - 01 June 2009, pp.87-93 identifier

  • Publication Type: Conference Paper / Full Text
  • City: İstanbul
  • Country: Turkey
  • Page Numbers: pp.87-93
  • Istanbul Technical University Affiliated: No


applications such as digital spectrum analyzers, digital filtering, image processing, and video transmission need to compute the Discrete Fourier Transfonn (DFT). A Chip architecture to compute a 64-point DFT using radix-4 algorithm every 18.87 mu s at 100MHz clock rate is designed. This processor incorporates static memory, controller, and combinational operating unit (COU). Input data and output data are 10-bit and 54-bit words, respectively. A 10-bit x 27-bit multiplier is used inside the processor. Two's complement is used to present negative data. This processor is implemented in 0.35 mu m tsmc standard CMOS process.