22nd European Signal Processing Conference (EUSIPCO), Lisbon, Portugal, 1 - 05 September 2014, pp.266-270
In this work, an FFT architecture supporting variable FFT sizes, 128 similar to 2048/1536, is proposed. This implementation is a combination of a 2(p) point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.