Linearly Weighted Classifier Circuit


Yildiz M., Minaei S., Oezoguz S.

Joint IEEE North-East Workshop on Circuits and Systems/TAISA Conference 2009, Toulouse, France, 28 June - 01 July 2009, pp.77-78 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Toulouse
  • Country: France
  • Page Numbers: pp.77-78

Abstract

In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of Linearly Weighted Circuits (LWC) and CMOS Core Circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 mu m AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.