Energy Saving Potential of Low-Temperature Cooling of Computers

Khalifa H. E., Erden H. S., de Rouge R. B.

14th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Florida, United States Of America, 27 - 30 May 2014, pp.1121-1128 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/itherm.2014.6892406
  • City: Florida
  • Country: United States Of America
  • Page Numbers: pp.1121-1128
  • Istanbul Technical University Affiliated: No


Current trends in data center cooling infrastructure design drive toward raising the coolant temperature to as high a level as equipment reliability allows in order to reduce the energy consumed by the cooling infrastructure and, consequently, improve (i.e., decrease) the power utilization effectiveness (PUE). However, as currently applied, PUE would appear to have deteriorated if measures are taken to reduce the energy consumption of the servers themselves. Because the temperature-dependent leakage power dissipation of modern deep-submicron computer chips constitutes a large fraction of the total power dissipation of these chips, the power consumption of such chips can be reduced by operating them at lower temperature. Not only does low-temperature operation reduce leakage power dissipation, but also it increases reliability and opens the potential for increasing the chip clock speed. However, these benefits may not lead to a reduction in the overall power consumption of the system of the servers and their associated cooling infrastructure if the leakage power reductions are more than offset by an increase in the power consumption of the low - temperature cooling infrastructure. In this paper we present a preliminary analytical study of a power and refrigeration cascade system (PARCS) that has the potential to realize the benefits of chip low temperature operation while decreasing the overall power consumption of the servers and their cooling infrastructure. We describe a parametric conceptual model of the combined servers and PARCS as a function of the coolant temperature and show that the optimum coolant temperature of servers equipped with 45, 32 and 22 nm chips could be substantially lower than the 27 degrees C recommended by ASHRAE.